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Efficient FPGA Binary Neural Network Architecture for Image Super-Resolution
Journal article   Open access   Peer reviewed

Efficient FPGA Binary Neural Network Architecture for Image Super-Resolution

Yuanxin Su, Kah Phooi Seng, Jeremy Smith and Li Minn Ang
Electronics, Vol.13(2), pp.1-16
2024
DOI: https://doi.org/10.3390/electronics13020266
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Efficient FPGA Binary Neural Network Architecture for Image Super-Resolution1.99 MBDownloadView
Published VersionCC BY V4.0,  Open Access

Abstract

field programmable gate array (FPGA) binary neural network (BNN) deep learning hardware architecture image super-resolution
Super-resolution systems refer to computer-based systems designed to enhance the quality of images or video by producing high-resolution renditions from low-resolution counterparts using computational algorithms and technologies. Various methods and techniques have been used in development of super-resolution systems. The development of Convolution Neural Networks (CNNs) and the Deep Learning (DL) methods have outperformed traditional methods. However, as models become increasingly deeper with wider receptive fields, the number of parameters significantly increases. While this often results in better performance, it renders these models impractical for real-life scenarios such as smartphones or other mobile systems. Currently, most proposed methods with higher perceptual quality demand a substantial amount of time to process a single image, even on powerful hardware like NVIDIA GPUs. Such computationally expensive models are not cost-effective for real-world application scenarios. Optimization is needed to reduce the computational costs and memory requirements to enhance their suitability for less powerful hardware configurations. In this work, we propose an efficient binary neural network architecture, ResBinESPCN, designed for image super-resolution. In our design, we improved the energy efficiency of the architecture through algorithmic and hardware-level optimizations. These optimizations not only enhance computational efficiency and reduce memory consumption but also achieve effective image super-resolution in resource-constrained environments. Our experimental validation highlights the effectiveness of this network structure and includes ablation studies on models with varying data bit widths. Hardware analysis substantiates the efficiency and real-time capabilities of this model. Additionally, deploying the model on FPGA using FINN demonstrates its low hardware resource usage and low power consumption.

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