Journal article
Compilation techniques for high level parallel code
International Journal of Parallel Programming, Vol.38(1), pp.4-18
2010
Abstract
This paper describes methods to adapt existing optimizing compilers for sequential languages to produce code for parallel processors. In particular it looks at targeting data-parallel processors using SIMD (single instruction multiple data) or vector processors where users need features similar to high-level control flow across the data-parallelism. The premise of the paper is that we do not want to write an optimizing compiler from scratch. Rather, a method is described that allows a developer to take an existing compiler for a sequential language and modify it to handle SIMD extensions. As well as modifying the front-end, the intermediate representation and the code generation to handle the parallelism, specific optimizations are described to target the architecture efficiently. © 2009 Springer Science+Business Media, LLC.
Details
- Title
- Compilation techniques for high level parallel code
- Authors
- B R Gaster (Author) - AMD, United StatesT Bainbridge (Author) - ClearSpeed Technology Plc, United KingdomDavid Lacey (Author) - XMOs Semiconductor, United KingdomD Gardner (Author) - XMOs Semiconductor, United Kingdom
- Publication details
- International Journal of Parallel Programming, Vol.38(1), pp.4-18
- Publisher
- Springer New York LLC
- Date published
- 2010
- DOI
- 10.1007/s10766-009-0118-5
- ISSN
- 0885-7458
- Organisation Unit
- Cyber Institute; University of the Sunshine Coast, Queensland
- Language
- English
- Record Identifier
- 99449398502621
- Output Type
- Journal article
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