VLSI decoder architecture for embedded zerotree wavelet algorithm

Li-Minn Ang; Hon Nin Cheung; K Eshraghian

doi:10.1109/ISCAS.1999.777823

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VLSI decoder architecture for embedded zerotree wavelet algorithm

Conference paper

Peer reviewed

VLSI decoder architecture for embedded zerotree wavelet algorithm

Li-Minn Ang, Hon Nin Cheung and K Eshraghian

IEEE International Symposium on Circuits and Systems, pp.I-141-I-144

IEEE International Symposium on Circuits and Systems (ISCAS), 1999 (Orlando, United States, 30-May-1999–02-Jun-1999)

Institute of Electrical and Electronics Engineers

1999

DOI: https://doi.org/10.1109/ISCAS.1999.777823

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Abstract

Decoder architecture

Embedded zerotree wavelet algorithm

Successive approximation quantization symbols

Algorithms

Application specific integrated circuits

Approximation theory

Decoding

Image coding

Wavelet transforms

VLSI circuits

In this paper, we present a hardware architecture to implement the decoder for the embedded zerotree wavelet (EZW) algorithm. The decoder architecture complements an encoder architecture for the EZW algorithm which has been reported recently. Similar to the reported encoder architecture, the proposed decoder architecture is regular and modular and is suitable for VLSI implementation. The input into the decoder architecture is the output data stream from the encoder architecture containing the-significance map symbols and the successive-approximation quantization symbols of the EZW algorithm. The decoding for the EZW algorithm is formulated in view of the output data stream from the encoder and the corresponding VLSI architecture to implement the formulated requirements is presented. The proposed EZW decoder architecture together with th_e encoder architecture forms a basis for a scalable image or'video coding system which is suitable for ASIC VLSI implementation.

Details

Title: VLSI decoder architecture for embedded zerotree wavelet algorithm
Authors: Li-Minn Ang (Author) - Edith Cowan University
Hon Nin Cheung (Author) - Edith Cowan University
K Eshraghian (Author) - Edith Cowan University
Publication details: IEEE International Symposium on Circuits and Systems, pp.I-141-I-144
Conference details: IEEE International Symposium on Circuits and Systems (ISCAS), 1999 (Orlando, United States, 30-May-1999–02-Jun-1999)
Publisher: Institute of Electrical and Electronics Engineers
Date published: 1999
DOI: 10.1109/ISCAS.1999.777823
ISSN: 0271-4310
Organisation Unit: University of the Sunshine Coast, Queensland; School of Science, Technology and Engineering; Engage Research Lab
Language: English
Record Identifier: 99513895002621
Output Type: Conference paper

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