Conference paper
Minimal instruction set AES processor using Harvard architecture
2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, Vol.9, pp.65-69
International Conference on Computer Science and Information Technology, 3rd (Chengdu, China, 09-Jul-2010–11-Jul-2010)
Institute of Electrical and Electronics Engineers
2010
Abstract
This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1% of the total available chip area.
Details
- Title
- Minimal instruction set AES processor using Harvard architecture
- Authors
- J H Kong (Author) - University of Nottingham Malaysia CampusL-M Ang (Author) - University of Nottingham Malaysia CampusK P Seng (Author) - University of Nottingham Malaysia Campus
- Publication details
- 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, Vol.9, pp.65-69
- Conference details
- International Conference on Computer Science and Information Technology, 3rd (Chengdu, China, 09-Jul-2010–11-Jul-2010)
- Publisher
- Institute of Electrical and Electronics Engineers
- Date published
- 2010
- DOI
- 10.1109/ICCSIT.2010.5564522
- ISBN
- 9781424455409
- Organisation Unit
- University of the Sunshine Coast, Queensland; School of Science, Technology and Engineering; Engage Research Lab
- Language
- English
- Record Identifier
- 99513901602621
- Output Type
- Conference paper
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