Conference paper
Implementation of (15, 9) Reed Solomon Minimal Instruction set computing on FPGA using handel-C
2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010, pp.356-361
International Conference on Computer Applications and Industrial Electronics (ICCAIE 2010), 2010 (Kuala Lumpur, Malaysia, 05-Dec-2010–08-Dec-2010)
Institute of Electrical and Electronics Engineers
2010
Abstract
Reed Solomon coding has an important role to play as to sustain reliability of data communication. However, the encoder consumes significant amount of power that affects the cost of producing the hardware. Besides, the complicated encoder circuit also does affect the cost of implemented hardware. There is a need to build a simple encoder which does the similar data encoding function. By amalgamate One Instruction Set Computer (OISC) and the Galois Field arithmetic, a Reed Solomon Minimal Instruction Computer (MISC) processor is developed. This processor has simpler circuit that still has the same encoded codeword produced.
Details
- Title
- Implementation of (15, 9) Reed Solomon Minimal Instruction set computing on FPGA using handel-C
- Authors
- J J Ong (Author) - University of Nottingham Malaysia CampusLi-Minn Ang (Author) - University of Nottingham Malaysia CampusK P Seng (Author) - University of Nottingham Malaysia Campus
- Publication details
- 2010 International Conference on Computer Applications and Industrial Electronics, ICCAIE 2010, pp.356-361
- Conference details
- International Conference on Computer Applications and Industrial Electronics (ICCAIE 2010), 2010 (Kuala Lumpur, Malaysia, 05-Dec-2010–08-Dec-2010)
- Publisher
- Institute of Electrical and Electronics Engineers
- Date published
- 2010
- DOI
- 10.1109/ICCAIE.2010.5735103
- ISBN
- 9781424490547
- Organisation Unit
- University of the Sunshine Coast, Queensland; School of Science, Technology and Engineering; Engage Research Lab
- Language
- English
- Record Identifier
- 99513902102621
- Output Type
- Conference paper
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